The present invention relates generally to semiconductors and more specifically to seed materials used in semiconductor processing.
In the process of manufacturing integrated circuits, after the individual devices, such as the transistors, have been fabricated in the silicon substrate, they must be connected together to perform the desired circuit functions. This connection process is generally called xe2x80x9cmetalizationxe2x80x9d, and is performed using a number of different photolithographic and deposition techniques.
One metalization process, which is called the xe2x80x9cdamascenexe2x80x9d technique starts with the placement of a first channel dielectric layer, which is typically an oxide layer, over the semiconductor devices. A first damascene step photoresist is then placed over the oxide layer and is photolithographically processed to form the pattern of the first channels. An anisotropic oxide etch is then used to etch out the channel oxide layer to form the first channel openings. The damascene step photoresist is stripped and a barrier layer is deposited to coat the walls of the first channel opening to ensure good adhesion and to act as a barrier material to prevent diffusion of such conductive material into the oxide layer and the semiconductor devices (the combination of the adhesion and barrier material is collectively referred to as xe2x80x9cbarrier layerxe2x80x9d herein). A seed layer is then deposited on the barrier layer to form a conductive material base, or xe2x80x9cseedxe2x80x9d, for subsequent deposition of conductive material. A conductive material is then deposited in the first channel openings and subjected to a chemical-mechanical polishing process which removes the first conductive material above the first channel oxide layer and damascenes the conductive material in the first channel openings to form the first channels.
For multiple layers of channels, another metalization process, which is called the xe2x80x9cdual damascenexe2x80x9d technique, is used in which the channels and vias are formed at the same time. In one example, the via formation step of the dual damascene technique starts with the deposition of a thin stop nitride over the first channels and the first channel oxide layer. Subsequently, a separating oxide layer is deposited on the stop nitride. This is followed by deposition of a thin via nitride. Then a via step photoresist is used in a photolithographic process to designate round via areas over the first channels.
A nitride etch is then used to etch out the round via areas in the via nitride. The via step photoresist is then removed, or stripped. A second channel dielectric layer, which is typically an oxide layer, is then deposited over the via nitride and the exposed oxide in the via area of the via nitride. A second damascene step photoresist is placed over the second channel oxide layer and is photolithographically processed to form the pattern of the second channels. An anisotropic oxide etch is then used to etch the second channel oxide layer to form the second channel openings and, during the same etching process to etch the via areas down to the thin stop nitride layer above the first channels to form the via openings. The damascene photoresist is then removed, and a nitride etch process removes the nitride above the first channels in the via areas. A barrier layer is then deposited to coat the via openings and the second channel openings. Next, a seed layer is deposited on the barrier layer. This is followed by a electroplating of the conductive material on the seed layer in the second channel openings and the via openings to form the second channel and the via. A second chemical-mechanical polishing process leaves the two vertically separated, horizontally perpendicular channels connected by a cylindrical via.
The use of the damascene techniques eliminates metal etch and dielectric gap fill steps typically used in the metalization process. The elimination of metal etch steps is important as the semiconductor industry moves from aluminum to other metalization materials, such as copper, which are very difficult to etch.
One drawback of using copper is that copper diffuses rapidly through various materials. Unlike aluminum, copper also diffuses through dielectrics, such as oxide. When copper diffuses through dielectrics, it can cause damage to neighboring devices on the semiconductor substrate. To prevent diffusion, materials such as tantalum nitride (TaN), titanium nitride (TiN), or tungsten nitride (VN) are used as barrier materials for copper. A thin adhesion layer formed of an adhesion material, such as the unnitrided form of the barrier material, is often first deposited on the dielectrics or vias to ensure good adhesion and good electrical contact of the subsequently deposited seed layers to underlying doped regions and/or conductive channels. Adhesion/barrier layer stacks formed of adhesion/barrier materials such as tantalum/tantalum nitride (Ta/TaN), titaniumn/titanium nitride (Ti/TiN), or just tungsten nitride (WN) have been found to be useful as adhesion/barrier material combination for copper interconnects.
The difficulty with nitride-containing barrier materials is that conductive materials such as copper often do not have good adhesion with these materials. With poor adhesion, there is a greater likelihood of electro-migration of the conductive material under load and the formation of voids which can cause increased resistance or open circuit failures.
Thus, a solution which would allow good adhesion of the copper seed to the barrier layer while providing a high conductive surface for following electroplating of conductive material has long been sought, but has eluded those skilled in the art. As the semiconductor industry moves from aluminum to copper and other types of materials with greater electroconductivity and diffusiveness through dielectrics, it has become more pressing that a solution be found.
The present invention provides a method for forming semiconductor seed layers of graded conductor alloys with barrier layer elements to provide good adhesion of the conductive layer to the barrier layer.
The present invention provides a method for forming seed layers of conductive metal alloyed with one of the metals including tin, magnesium, and aluminum with various concentrations of nitrogen.
The present invention provides a method for forming seed layers of conductive metal alloyed with one of the metals including tin, magnesium, and aluminum with the highest concentration of nitrogen proximate the barrier layer.
The present invention provides a method for forming semiconductor copper seed layers with the copper alloyed with one of the metals from the group comprising tin, magnesium, and aluminum. The alloy further has a graded nitrogen content with the highest concentration of nitrogen proximate the tungsten nitride barrier layer. The high concentration of nitrogen in the copper alloy provides good adhesion of the seed layer to the barrier layer while the lack of nitrogen distal from the barrier layer allows the copper conductive to have good adhesion with the pure copper conductive material.
The present invention provides for good adhesion for the seed layer both for the barrier layer and the conductive layer.
The present invention further provides a seed layer having good adhesion to both the barrier layer and the conductive layer so as to decrease electro-migration.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.